The Application of NanoTime in High Speed SRAM IP Designing with 65nm Process

Computer & Telecommunication

2017, Vol. 1

Issue (7): 51-55 DOI:

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The Application of NanoTime in High Speed SRAM IP Designing with 65nm Process

Zhang Jiaxun

Shenzhen State Microelectronics Co.,Ltd.

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Abstract As the IC process below 90nm, nanometer effect is more evident. For custom digital logic, how to analyze Signal Integrity (SI) is very important. The high speed SRAM IP is designed by 65nm process. Our design team used NanoTime for signal integrity checking. This paper introduces NanoTime application of static timing analysis, timing model generation and SI analysis in the high speed SRAM IP design.

Key words： NanoTime static timing analysis SI analysis timing model generation

Published: 16 November 2017

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Zhang Jiaxun. The Application of NanoTime in High Speed SRAM IP Designing with 65nm Process. Computer & Telecommunication, 2017, 1(7): 51-55.

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https://www.computertelecom.com.cn/EN/ OR https://www.computertelecom.com.cn/EN/Y2017/V1/I7/51

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